Fast ADC / 2nd Detector Overview

The N2PK VNA, as described in the Part 1 & Part 2 PDFs, uses the LTC2410 24 bit ADC, herein referred to as the 'slow' ADC. This ADC has a nominal 133.5 ms conversion time or, equivalently, a rate of 7.5 conversions/sec when using the internal clock set for a notch at 60 Hz.

As also indicated in Part 2 (pg 18), development of a 2nd detector for the VNA is underway to "provide the user with frequency sweeps fast enough to allow data at hundreds of frequencies to be displayed on the PC screen at sub-second refresh rates. This would provide a much-improved facility for real-time measurements and adjustments. The higher speed will result in less dynamic range, but that is typically an acceptable trade-off to obtain real-time adjustment of things like filter passband noses or return loss that may be only 30 to 40 dB."

At the time Part 2 was written, an ADC candidate to do this had been identified and its parallel port assignments had already been reflected in my parallel port test program, "PARPORT". This ADC had several differences in architecture from the slow ADC and also offered fewer bits.

In Jan. 2004, I found the LTC2440 ADC, 24 bits like the slow ADC, which also offered substantially improved conversion rates over the slow ADC. The LTC2440 conversion rate can be controlled via a new Serial Data In (SDI) line which is not present on the slow ADC. The raw conversion rate of the LTC2440 can range from nearly the same as the slow ADC to 470 times faster with eight rates in between.

The LTC2440 is also nearly pin-compatible with the slow ADC. This was an attractive feature as it offered the possibility of being a drop-in replacement for the slow ADC on the 1st detector, along with some new components, some component changes, and wire mods that could all be handled using the existing PCB.

The combination of all these features was so attractive that the LTC2440 was ordered and development of the 2nd detector then centered around the LTC2440 ADC, herein referred to as the 'fast' ADC.

That development has proceeded to the point where a 2nd detector using the fast ADC has been built on a 2nd VNA PCB and incorporated into my "PCB VNA" as shown on pg 20 of Part 2. Rather than lay out a new PCB, the original PCB was used for this 2nd detector, but without the DDSs, master oscillator, and other associated components populated on it.

In addition, the fast ADC has been retro-fitted into the only detector in my prototype VNA which also originally had the slow ADC.

Some of my VNA software has been updated to utilize either the fast or the slow ADC in either or both detectors. This software along with build/mod instructions is out for beta test now.

The slow ADC has remained in the 1st detector of my PCB VNA while the 2nd detector uses the fast ADC. This was done to permit evaluation of concerns I had regarding loss of dynamic range and increased interference potential with external signals, as may be present in antenna measurements, and widened analog bandwidth needed to support the fast ADC running at its highest rate. While changing analog bandwidth with ADC rate could be done, the added level of complexity and hardware mods needed to do this were not deemed generally desirable.

Preserving the slow ADC in one detector also allows me to ensure backward hardware compatibility as I develop new software. I do not intend to leave existing VNA users 'out in the cold.' While there are clearly some features in the new software that a VNA with the slow ADC will not take advantage of, such as the higher conversion rates, there are other desirable software changes that can be useful.

Completing all this takes time - always more than I anticipate - at least to do it with attention to detail.

While the beta testing is not yet complete, there have been some recent activities by several other N2PK VNA users that have given me reason to break from my inclination not to generally publicize, in detail, new features and hardware changes without being reasonably sure that these changes will be stable. Normally I have relied on a trusted group of beta testers that a) would not pre-maturely disseminate information, and b) understand that beta testing does carry a risk that some things might change in a substantive way.

Since some of these users are planning different hardware changes & have different objectives - both of which potentially conflict with my changes & additions, I have decided to forego my inclination at this point in order to provide all users with more information to better assess which way they would like to go as they see various options from various users emerge.

So, what follows below is to be interpreted as a "statement of intent" which comes without a guarantee that all will come to pass precisely as layed out here. I will also try to keep users abreast of any substantive changes to this, should they occur.

The fast ADC and 2nd VNA detector are part of a larger plan to implement an 'Expanded N2PK VNA' which would have two receivers (detectors) and a full-featured S-parameter test set. The aim is to do this while still providing software support of back level hardware wherever possible.

Key hardware features of the 'Expanded N2PK VNA' are planned to be:

  • the existing two DDS sources,
  • the fast ADC in the 1st Detector,
  • the fast ADC in the 2nd Detector,
  • independent rate control of the fast ADC in either detector,
  • equal maximum performance of the fast ADCs in both detectors,
  • the use of one detector for reflection and the other for transmission, (may not be the same detector for forward and reverse directions in the S-parameter test set below),
  • equal max. performance of the fast ADCs in both detectors,
  • interface simplicity directly to unique or orthogonal hardware functions, and
  • simple directional control of an S-parameter test set, if present. which also contains DC bias insertion on both ports and also a step attenuator (likely 0 - 70 dB in 10 dB steps).

Key software support & features for the 'Expanded N2PK VNA' are planned to be:

  • Real time graphics,
  • Existing two DDS sources,
  • Either the fast (rate controlled) or the slow ADC in either detector,
  • One or both detectors in any given VNA,
  • Simple directional and attenuator control in the S-parameter test set, if present
  • Improved transmission calibration methods, likely including 12-term error correction if the S-Parameter test set is present,
  • Overlapping data collection from both detectors for reduced test time and real time graphics update rate.
  • Sub-ms settling time.

Here is a screenshot from one of the new real time graphics programs with the Fast detector running at its highest rate (90 dB dynamic range):

@ Rate=10

Real Time graphics will include many new features, such as:

  • Fastest sweeps occur at 900 frequencies/sec, enabling real time adjustments with graphical display
  • Single/Continuous Sweep & Sweep Pause
  • Auto and manual plot scaling
  • Storage scope mode - multiple sweeps displayed and the last highlighted,
  • Erase - primarily for storage mode
  • Markers On/Off
  • Markers Left/Right
  • Reference sweep
  • Save current sweep

To see my planned parallel port assignments to support the "Expanded N2PK VNA', click here.

Key features of the Fast ADC in either detector are:

  • Uses the internal ADC clock
  • Support for all ten ADC conversion rates ranging from 6.875 conversions/sec (145.5 ms/conversion) to 3520 conversions/sec (0.284 ms/conversion).
  • Fixed analog bandwidth preceeding the ADC.
  • System dynamic range ranging from about 122 dB at the slowest rate to 90 dB at the highest rate without averaging. This presumes a high quality master oscillator like the Valpey Fisher or the homebrew oscillator. This allows the user to reduce test time at the expense of dynamic range.
  • 50/60 Hz rejection is only provided at the slowest ADC rate.
  • Narrowband detector - ADC digitally controlled 3 dB bandwidth (around DDS center frequency) ranges from 6.6 Hz at slowest ADC rate to 3400 Hz at the highest rate.
  • Minor modifications to retro-fit an existing Detector.
  • Common PCB

Please feel free to contact me with any comments or questions at:


Paul Kiciak, N2PK

Last updated: 19 Oct. 2006
Copyright © 2003 - 2006